1. Field of the Invention
This invention relates to high performance computing network systems, and more particularly, to clock and data recovery methods for systems using serialized data transmission.
2. Description of the Relevant Art
The performance of computing systems is dependent on both hardware and software. In order to increase the throughput of computing systems, the parallelization of tasks is utilized as much as possible. To this end, compilers may extract parallelized tasks from program code and hardware may include multiple copies of structures to execute the parallelized tasks. The structures may include functional units, processor cores, and nodes.
Communication between the multiple structures may utilize wide communication buses, i.e., buses that transport data words of 16-bits, 32-bits, 64-bits, or more in parallel. The physical implementation of such communication buses may consume significant area/cost on an integrated circuit (IC), a circuit board or in cables between circuit boards. Additionally, cross-capacitance, electromagnetic interference (EMI), and parasitic inductance on wide buses increase the power consumption and noise effects of the computing system. Such parasitic effects may become more pronounced with increased operational frequencies and reduced geometric dimensions of the wide buses themselves, bond wires, integrated circuit (IC) package leads, and external supply lines. Mismatch of impedance values at the end of transmission lines may result in reflection or ringing, increased propagation delays, and voltage droop of the signals being transmitted.
Reducing the problems with high-speed parallel data transmission may include use of high-speed serial communication. Several examples of high-speed serial communications standards include wired standards, such as, Ethernet, Universal Serial Bus (USB, and USB 3.0 in particular), and Serial AT Attachment (SATA). While these examples typically involve communication over a length of cable between two circuit boards, high-speed serial communications may be used between devices on a common circuit board or between functional blocks within a single IC. Serial communication is also used in wireless standards, such as Wi-Fi™ and Bluetooth™. One way of further reducing communication lines and the associated issues is by eliminating a dedicated clock signal in the communication path. In some embodiments, a receiver may share a clock source with a transmitter and therefore may not require a separate clock signal. However, if a clock signal is not shared between a transmitter and a receiver, then a method for transmitting a clock signal from the transmitting circuit to the receiving circuit is required. One method for transmitting a clock signal is to embed the clock signal within the data stream.
A challenge may arise from variations of the duty cycle of a received stream of data bits from a transmitter. Generally speaking, a 50% duty cycle is desired such that the length of time each bit of data is valid is the same for each data bit. If the duty cycle deviates from 50% then the data bit valid times will alternate between being long and short. For example, in a 1 Gigabit per second (Gbps) communication link, a 50% duty cycle results in each data bit being valid for 1 nanosecond. If the duty cycle deviates to 60%, then the data bits will alternate between being valid for 1.2 nanoseconds and 0.8 nanoseconds. The shorter bit times may result in errors by the receiver reading the data.